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include
avr
wdt.h
Go to the documentation of this file.
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/* Copyright (c) 2002, 2004 Marek Michalkiewicz
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Copyright (c) 2005, 2006, 2007 Eric B. Weddington
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id: wdt.h 2211 2011-02-14 14:04:25Z aboyapati $ */
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/*
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avr/wdt.h - macros for AVR watchdog timer
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*/
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#ifndef _AVR_WDT_H_
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#define _AVR_WDT_H_
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#include <
avr/io.h
>
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#include <
stdint.h
>
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/** \file */
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/** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
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\code #include <avr/wdt.h> \endcode
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This header file declares the interface to some inline macros
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handling the watchdog timer present in many AVR devices. In order
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to prevent the watchdog timer configuration from being
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accidentally altered by a crashing application, a special timed
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sequence is required in order to change it. The macros within
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this header file handle the required sequence automatically
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before changing any value. Interrupts will be disabled during
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the manipulation.
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\note Depending on the fuse configuration of the particular
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device, further restrictions might apply, in particular it might
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be disallowed to turn off the watchdog timer.
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Note that for newer devices (ATmega88 and newer, effectively any
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AVR that has the option to also generate interrupts), the watchdog
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timer remains active even after a system reset (except a power-on
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condition), using the fastest prescaler value (approximately 15
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ms). It is therefore required to turn off the watchdog early
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during program startup, the datasheet recommends a sequence like
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the following:
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\code
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#include <stdint.h>
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#include <avr/wdt.h>
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uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
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void get_mcusr(void) \
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__attribute__((naked)) \
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__attribute__((section(".init3")));
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void get_mcusr(void)
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{
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mcusr_mirror = MCUSR;
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MCUSR = 0;
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wdt_disable();
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}
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\endcode
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Saving the value of MCUSR in \c mcusr_mirror is only needed if the
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application later wants to examine the reset source, but in particular,
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clearing the watchdog reset flag before disabling the
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watchdog is required, according to the datasheet.
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*/
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/**
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\ingroup avr_watchdog
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Reset the watchdog timer. When the watchdog timer is enabled,
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a call to this instruction is required before the timer expires,
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otherwise a watchdog-initiated device reset will occur.
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*/
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#define wdt_reset() __asm__ __volatile__ ("wdr")
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#if defined(WDP3)
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# define _WD_PS3_MASK _BV(WDP3)
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#else
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# define _WD_PS3_MASK 0x00
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#endif
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#if defined(WDTCSR)
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# define _WD_CONTROL_REG WDTCSR
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#else
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# define _WD_CONTROL_REG WDTCR
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#endif
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#if defined(WDTOE)
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#define _WD_CHANGE_BIT WDTOE
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#else
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#define _WD_CHANGE_BIT WDCE
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#endif
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/**
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\ingroup avr_watchdog
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Enable the watchdog timer, configuring it for expiry after
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\c timeout (which is a combination of the \c WDP0 through
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\c WDP2 bits to write into the \c WDTCR register; For those devices
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that have a \c WDTCSR register, it uses the combination of the \c WDP0
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through \c WDP3 bits).
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See also the symbolic constants \c WDTO_15MS et al.
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*/
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#if defined(__AVR_ATxmega16A4__) \
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|| defined(__AVR_ATxmega16D4__) \
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|| defined(__AVR_ATxmega32A4__) \
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|| defined(__AVR_ATxmega32D4__) \
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|| defined(__AVR_ATxmega64A1U__) \
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|| defined(__AVR_ATxmega64A3__) \
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|| defined(__AVR_ATxmega64D3__) \
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|| defined(__AVR_ATxmega128A1__) \
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|| defined(__AVR_ATxmega128A1U__) \
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|| defined(__AVR_ATxmega128A3__) \
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|| defined(__AVR_ATxmega128D3__) \
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|| defined(__AVR_ATxmega192A3__) \
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|| defined(__AVR_ATxmega192D3__) \
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|| defined(__AVR_ATxmega256A3__) \
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|| defined(__AVR_ATxmega256D3__) \
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|| defined(__AVR_ATxmega256A3B__)
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/*
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wdt_enable(WDT_PER_8KCLK_gc);
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*/
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#define wdt_enable(value) \
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__asm__ __volatile__ ( \
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"in __tmp_reg__, %0" "\n\t" \
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"out %1, %3" "\n\t" \
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"sts %2, %4" "\n\t" \
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"wdr" "\n\t" \
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"out %0, __tmp_reg__" "\n\t" \
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: \
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: "M" (_SFR_MEM_ADDR(RAMPD)), \
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"M" (_SFR_MEM_ADDR(CCP)), \
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"M" (_SFR_MEM_ADDR(WDT_CTRL)), \
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"r" ((uint8_t)0xD8), \
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"r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | value)) \
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: "r0" \
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)
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#elif defined(__AVR_AT90CAN32__) \
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|| defined(__AVR_AT90CAN64__) \
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|| defined(__AVR_AT90CAN128__) \
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|| defined(__AVR_AT90PWM1__) \
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|| defined(__AVR_AT90PWM2__) \
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|| defined(__AVR_AT90PWM216__) \
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|| defined(__AVR_AT90PWM2B__) \
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|| defined(__AVR_AT90PWM3__) \
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|| defined(__AVR_AT90PWM316__) \
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|| defined(__AVR_AT90PWM3B__) \
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|| defined(__AVR_AT90PWM81__) \
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|| defined(__AVR_AT90USB1286__) \
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|| defined(__AVR_AT90USB1287__) \
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|| defined(__AVR_AT90USB162__) \
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|| defined(__AVR_AT90USB646__) \
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|| defined(__AVR_AT90USB647__) \
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|| defined(__AVR_AT90USB82__) \
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|| defined(__AVR_ATmega1280__) \
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|| defined(__AVR_ATmega1281__) \
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|| defined(__AVR_ATmega1284P__) \
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|| defined(__AVR_ATmega128RFA1__) \
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|| defined(__AVR_ATmega1284RFR2__) \
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|| defined(__AVR_ATmega128RFR2__) \
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|| defined(__AVR_ATmega164__) \
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|| defined(__AVR_ATmega164A__) \
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|| defined(__AVR_ATmega164P__) \
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|| defined(__AVR_ATmega165__) \
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|| defined(__AVR_ATmega165A__) \
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|| defined(__AVR_ATmega165P__) \
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|| defined(__AVR_ATmega168__) \
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|| defined(__AVR_ATmega168A__) \
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|| defined(__AVR_ATmega168P__) \
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|| defined(__AVR_ATmega169__) \
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|| defined(__AVR_ATmega169A__) \
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|| defined(__AVR_ATmega169P__) \
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|| defined(__AVR_ATmega169PA__) \
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|| defined(__AVR_ATmega16HVA__) \
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|| defined(__AVR_ATmega16HVA2__) \
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|| defined(__AVR_ATmega16HVB__) \
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|| defined(__AVR_ATmega16HVBREVB__) \
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|| defined(__AVR_ATmega16M1__) \
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|| defined(__AVR_ATmega16U2__) \
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|| defined(__AVR_ATmega16U4__) \
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|| defined(__AVR_ATmega2560__) \
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|| defined(__AVR_ATmega2561__) \
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|| defined(__AVR_ATmega2564RFR2__) \
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|| defined(__AVR_ATmega256RFR2__) \
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|| defined(__AVR_ATmega324__) \
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|| defined(__AVR_ATmega324A__) \
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|| defined(__AVR_ATmega324P__) \
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|| defined(__AVR_ATmega324PA__) \
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|| defined(__AVR_ATmega325__) \
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|| defined(__AVR_ATmega325A__) \
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|| defined(__AVR_ATmega325P__) \
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|| defined(__AVR_ATmega3250__) \
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|| defined(__AVR_ATmega3250A__) \
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|| defined(__AVR_ATmega3250P__) \
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|| defined(__AVR_ATmega328__) \
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|| defined(__AVR_ATmega328P__) \
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|| defined(__AVR_ATmega329__) \
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|| defined(__AVR_ATmega329A__) \
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|| defined(__AVR_ATmega329P__) \
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|| defined(__AVR_ATmega329PA__) \
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|| defined(__AVR_ATmega3290__) \
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|| defined(__AVR_ATmega3290A__) \
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|| defined(__AVR_ATmega3290P__) \
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|| defined(__AVR_ATmega32C1__) \
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|| defined(__AVR_ATmega32HVB__) \
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|| defined(__AVR_ATmega32HVBREVB__) \
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|| defined(__AVR_ATmega32M1__) \
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|| defined(__AVR_ATmega32U2__) \
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|| defined(__AVR_ATmega32U4__) \
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|| defined(__AVR_ATmega32U6__) \
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|| defined(__AVR_ATmega406__) \
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|| defined(__AVR_ATmega48__) \
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|| defined(__AVR_ATmega48A__) \
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|| defined(__AVR_ATmega48P__) \
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|| defined(__AVR_ATmega644RFR2__) \
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|| defined(__AVR_ATmega64RFR2__) \
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|| defined(__AVR_ATmega640__) \
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|| defined(__AVR_ATmega644__) \
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|| defined(__AVR_ATmega644A__) \
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|| defined(__AVR_ATmega644P__) \
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|| defined(__AVR_ATmega644PA__) \
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|| defined(__AVR_ATmega645__) \
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|| defined(__AVR_ATmega645A__) \
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|| defined(__AVR_ATmega645P__) \
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|| defined(__AVR_ATmega6450__) \
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|| defined(__AVR_ATmega6450A__) \
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|| defined(__AVR_ATmega6450P__) \
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|| defined(__AVR_ATmega649__) \
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|| defined(__AVR_ATmega649A__) \
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|| defined(__AVR_ATmega6490__) \
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|| defined(__AVR_ATmega6490A__) \
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|| defined(__AVR_ATmega6490P__) \
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|| defined(__AVR_ATmega649P__) \
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|| defined(__AVR_ATmega64C1__) \
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|| defined(__AVR_ATmega64HVE__) \
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|| defined(__AVR_ATmega64M1__) \
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|| defined(__AVR_ATmega88__) \
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|| defined(__AVR_ATmega88A__) \
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|| defined(__AVR_ATmega88P__) \
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|| defined(__AVR_ATmega88PA__) \
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|| defined(__AVR_ATmega8HVA__) \
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|| defined(__AVR_ATmega8U2__) \
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|| defined(__AVR_ATtiny48__) \
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|| defined(__AVR_ATtiny88__) \
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|| defined(__AVR_ATtiny87__) \
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|| defined(__AVR_ATtiny167__) \
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|| defined(__AVR_AT90SCR100__) \
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|| defined(__AVR_ATA6289__)
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/* Use STS instruction. */
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#define wdt_enable(value) \
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__asm__ __volatile__ ( \
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"in __tmp_reg__,__SREG__" "\n\t" \
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"cli" "\n\t" \
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"wdr" "\n\t" \
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"sts %0,%1" "\n\t" \
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"out __SREG__,__tmp_reg__" "\n\t" \
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"sts %0,%2" "\n\t" \
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:
/* no outputs */
\
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: "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
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"r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
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"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
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_BV(WDE) | (value & 0x07)) ) \
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: "r0" \
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)
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#define wdt_disable() \
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__asm__ __volatile__ ( \
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"in __tmp_reg__, __SREG__" "\n\t" \
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"cli" "\n\t" \
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"sts %0, %1" "\n\t" \
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"sts %0, __zero_reg__" "\n\t" \
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"out __SREG__,__tmp_reg__" "\n\t" \
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:
/* no outputs */
\
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: "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
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"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
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: "r0" \
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)
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#else
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/* Use OUT instruction. */
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#define wdt_enable(value) \
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__asm__ __volatile__ ( \
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"in __tmp_reg__,__SREG__" "\n\t" \
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"cli" "\n\t" \
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"wdr" "\n\t" \
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"out %0,%1" "\n\t" \
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"out __SREG__,__tmp_reg__" "\n\t" \
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"out %0,%2" \
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:
/* no outputs */
\
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: "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
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"r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
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"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
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_BV(WDE) | (value & 0x07)) ) \
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: "r0" \
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)
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/**
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\ingroup avr_watchdog
337
Disable the watchdog timer, if possible. This attempts to turn off the
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Enable bit in the watchdog control register. See the datasheet for
339
details.
340
*/
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#define wdt_disable() \
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__asm__ __volatile__ ( \
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"in __tmp_reg__, __SREG__" "\n\t" \
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"cli" "\n\t" \
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"out %0, %1" "\n\t" \
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"out %0, __zero_reg__" "\n\t" \
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"out __SREG__,__tmp_reg__" "\n\t" \
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:
/* no outputs */
\
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: "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
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"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
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: "r0" \
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)
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#endif
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/**
359
\ingroup avr_watchdog
360
Symbolic constants for the watchdog timeout. Since the watchdog
361
timer is based on a free-running RC oscillator, the times are
362
approximate only and apply to a supply voltage of 5 V. At lower
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supply voltages, the times will increase. For older devices, the
364
times will be as large as three times when operating at Vcc = 3 V,
365
while the newer devices (e. g. ATmega128, ATmega8) only experience
366
a negligible change.
367
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Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
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500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
370
Symbolic constants are formed by the prefix
371
\c WDTO_, followed by the time.
372
373
Example that would select a watchdog timer expiry of approximately
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500 ms:
375
\code
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wdt_enable(WDTO_500MS);
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\endcode
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*/
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#define WDTO_15MS 0
380
381
/** \ingroup avr_watchdog
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See \c WDT0_15MS */
383
#define WDTO_30MS 1
384
385
/** \ingroup avr_watchdog See
386
\c WDT0_15MS */
387
#define WDTO_60MS 2
388
389
/** \ingroup avr_watchdog
390
See \c WDT0_15MS */
391
#define WDTO_120MS 3
392
393
/** \ingroup avr_watchdog
394
See \c WDT0_15MS */
395
#define WDTO_250MS 4
396
397
/** \ingroup avr_watchdog
398
See \c WDT0_15MS */
399
#define WDTO_500MS 5
400
401
/** \ingroup avr_watchdog
402
See \c WDT0_15MS */
403
#define WDTO_1S 6
404
405
/** \ingroup avr_watchdog
406
See \c WDT0_15MS */
407
#define WDTO_2S 7
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409
#if defined(__DOXYGEN__) || defined(WDP3)
410
411
/** \ingroup avr_watchdog
412
See \c WDT0_15MS
413
Note: This is only available on the
414
ATtiny2313,
415
ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
416
ATtiny25, ATtiny45, ATtiny85,
417
ATtiny261, ATtiny461, ATtiny861,
418
ATmega48, ATmega88, ATmega168,
419
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
420
ATmega164P, ATmega324P, ATmega644P, ATmega644,
421
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
422
ATmega8HVA, ATmega16HVA, ATmega32HVB,
423
ATmega406, ATmega1284P,
424
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
425
AT90PWM81,
426
AT90USB82, AT90USB162,
427
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
428
ATtiny48, ATtiny88.
429
*/
430
#define WDTO_4S 8
431
432
/** \ingroup avr_watchdog
433
See \c WDT0_15MS
434
Note: This is only available on the
435
ATtiny2313,
436
ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
437
ATtiny25, ATtiny45, ATtiny85,
438
ATtiny261, ATtiny461, ATtiny861,
439
ATmega48, ATmega88, ATmega168,
440
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
441
ATmega164P, ATmega324P, ATmega644P, ATmega644,
442
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
443
ATmega8HVA, ATmega16HVA, ATmega32HVB,
444
ATmega406, ATmega1284P,
445
ATmega2564RFR2, ATmega256RFR2, ATmega1284RFR2, ATmega128RFR2, ATmega644RFR2, ATmega64RFR2
446
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
447
AT90PWM81,
448
AT90USB82, AT90USB162,
449
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
450
ATtiny48, ATtiny88.
451
*/
452
#define WDTO_8S 9
453
454
#endif
/* defined(__DOXYGEN__) || defined(WDP3) */
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#endif
/* _AVR_WDT_H_ */
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