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wdt.h
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1 /* Copyright (c) 2002, 2004 Marek Michalkiewicz
2  Copyright (c) 2005, 2006, 2007 Eric B. Weddington
3  All rights reserved.
4 
5  Redistribution and use in source and binary forms, with or without
6  modification, are permitted provided that the following conditions are met:
7 
8  * Redistributions of source code must retain the above copyright
9  notice, this list of conditions and the following disclaimer.
10 
11  * Redistributions in binary form must reproduce the above copyright
12  notice, this list of conditions and the following disclaimer in
13  the documentation and/or other materials provided with the
14  distribution.
15 
16  * Neither the name of the copyright holders nor the names of
17  contributors may be used to endorse or promote products derived
18  from this software without specific prior written permission.
19 
20  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  POSSIBILITY OF SUCH DAMAGE. */
31 
32 /* $Id: wdt.h 2211 2011-02-14 14:04:25Z aboyapati $ */
33 
34 /*
35  avr/wdt.h - macros for AVR watchdog timer
36  */
37 
38 #ifndef _AVR_WDT_H_
39 #define _AVR_WDT_H_
40 
41 #include <avr/io.h>
42 #include <stdint.h>
43 
44 /** \file */
45 /** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
46  \code #include <avr/wdt.h> \endcode
47 
48  This header file declares the interface to some inline macros
49  handling the watchdog timer present in many AVR devices. In order
50  to prevent the watchdog timer configuration from being
51  accidentally altered by a crashing application, a special timed
52  sequence is required in order to change it. The macros within
53  this header file handle the required sequence automatically
54  before changing any value. Interrupts will be disabled during
55  the manipulation.
56 
57  \note Depending on the fuse configuration of the particular
58  device, further restrictions might apply, in particular it might
59  be disallowed to turn off the watchdog timer.
60 
61  Note that for newer devices (ATmega88 and newer, effectively any
62  AVR that has the option to also generate interrupts), the watchdog
63  timer remains active even after a system reset (except a power-on
64  condition), using the fastest prescaler value (approximately 15
65  ms). It is therefore required to turn off the watchdog early
66  during program startup, the datasheet recommends a sequence like
67  the following:
68 
69  \code
70  #include <stdint.h>
71  #include <avr/wdt.h>
72 
73  uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
74 
75  void get_mcusr(void) \
76  __attribute__((naked)) \
77  __attribute__((section(".init3")));
78  void get_mcusr(void)
79  {
80  mcusr_mirror = MCUSR;
81  MCUSR = 0;
82  wdt_disable();
83  }
84  \endcode
85 
86  Saving the value of MCUSR in \c mcusr_mirror is only needed if the
87  application later wants to examine the reset source, but in particular,
88  clearing the watchdog reset flag before disabling the
89  watchdog is required, according to the datasheet.
90 */
91 
92 /**
93  \ingroup avr_watchdog
94  Reset the watchdog timer. When the watchdog timer is enabled,
95  a call to this instruction is required before the timer expires,
96  otherwise a watchdog-initiated device reset will occur.
97 */
98 
99 #define wdt_reset() __asm__ __volatile__ ("wdr")
100 
101 
102 #if defined(WDP3)
103 # define _WD_PS3_MASK _BV(WDP3)
104 #else
105 # define _WD_PS3_MASK 0x00
106 #endif
107 
108 #if defined(WDTCSR)
109 # define _WD_CONTROL_REG WDTCSR
110 #else
111 # define _WD_CONTROL_REG WDTCR
112 #endif
113 
114 #if defined(WDTOE)
115 #define _WD_CHANGE_BIT WDTOE
116 #else
117 #define _WD_CHANGE_BIT WDCE
118 #endif
119 
120 
121 /**
122  \ingroup avr_watchdog
123  Enable the watchdog timer, configuring it for expiry after
124  \c timeout (which is a combination of the \c WDP0 through
125  \c WDP2 bits to write into the \c WDTCR register; For those devices
126  that have a \c WDTCSR register, it uses the combination of the \c WDP0
127  through \c WDP3 bits).
128 
129  See also the symbolic constants \c WDTO_15MS et al.
130 */
131 
132 
133 #if defined(__AVR_ATxmega16A4__) \
134 || defined(__AVR_ATxmega16D4__) \
135 || defined(__AVR_ATxmega32A4__) \
136 || defined(__AVR_ATxmega32D4__) \
137 || defined(__AVR_ATxmega64A1U__) \
138 || defined(__AVR_ATxmega64A3__) \
139 || defined(__AVR_ATxmega64D3__) \
140 || defined(__AVR_ATxmega128A1__) \
141 || defined(__AVR_ATxmega128A1U__) \
142 || defined(__AVR_ATxmega128A3__) \
143 || defined(__AVR_ATxmega128D3__) \
144 || defined(__AVR_ATxmega192A3__) \
145 || defined(__AVR_ATxmega192D3__) \
146 || defined(__AVR_ATxmega256A3__) \
147 || defined(__AVR_ATxmega256D3__) \
148 || defined(__AVR_ATxmega256A3B__)
149 
150 /*
151  wdt_enable(WDT_PER_8KCLK_gc);
152 */
153 #define wdt_enable(value) \
154 __asm__ __volatile__ ( \
155  "in __tmp_reg__, %0" "\n\t" \
156  "out %1, %3" "\n\t" \
157  "sts %2, %4" "\n\t" \
158  "wdr" "\n\t" \
159  "out %0, __tmp_reg__" "\n\t" \
160  : \
161  : "M" (_SFR_MEM_ADDR(RAMPD)), \
162  "M" (_SFR_MEM_ADDR(CCP)), \
163  "M" (_SFR_MEM_ADDR(WDT_CTRL)), \
164  "r" ((uint8_t)0xD8), \
165  "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | value)) \
166  : "r0" \
167 )
168 
169 
170 #elif defined(__AVR_AT90CAN32__) \
171 || defined(__AVR_AT90CAN64__) \
172 || defined(__AVR_AT90CAN128__) \
173 || defined(__AVR_AT90PWM1__) \
174 || defined(__AVR_AT90PWM2__) \
175 || defined(__AVR_AT90PWM216__) \
176 || defined(__AVR_AT90PWM2B__) \
177 || defined(__AVR_AT90PWM3__) \
178 || defined(__AVR_AT90PWM316__) \
179 || defined(__AVR_AT90PWM3B__) \
180 || defined(__AVR_AT90PWM81__) \
181 || defined(__AVR_AT90USB1286__) \
182 || defined(__AVR_AT90USB1287__) \
183 || defined(__AVR_AT90USB162__) \
184 || defined(__AVR_AT90USB646__) \
185 || defined(__AVR_AT90USB647__) \
186 || defined(__AVR_AT90USB82__) \
187 || defined(__AVR_ATmega1280__) \
188 || defined(__AVR_ATmega1281__) \
189 || defined(__AVR_ATmega1284P__) \
190 || defined(__AVR_ATmega128RFA1__) \
191 || defined(__AVR_ATmega1284RFR2__) \
192 || defined(__AVR_ATmega128RFR2__) \
193 || defined(__AVR_ATmega164__) \
194 || defined(__AVR_ATmega164A__) \
195 || defined(__AVR_ATmega164P__) \
196 || defined(__AVR_ATmega165__) \
197 || defined(__AVR_ATmega165A__) \
198 || defined(__AVR_ATmega165P__) \
199 || defined(__AVR_ATmega168__) \
200 || defined(__AVR_ATmega168A__) \
201 || defined(__AVR_ATmega168P__) \
202 || defined(__AVR_ATmega169__) \
203 || defined(__AVR_ATmega169A__) \
204 || defined(__AVR_ATmega169P__) \
205 || defined(__AVR_ATmega169PA__) \
206 || defined(__AVR_ATmega16HVA__) \
207 || defined(__AVR_ATmega16HVA2__) \
208 || defined(__AVR_ATmega16HVB__) \
209 || defined(__AVR_ATmega16HVBREVB__) \
210 || defined(__AVR_ATmega16M1__) \
211 || defined(__AVR_ATmega16U2__) \
212 || defined(__AVR_ATmega16U4__) \
213 || defined(__AVR_ATmega2560__) \
214 || defined(__AVR_ATmega2561__) \
215 || defined(__AVR_ATmega2564RFR2__) \
216 || defined(__AVR_ATmega256RFR2__) \
217 || defined(__AVR_ATmega324__) \
218 || defined(__AVR_ATmega324A__) \
219 || defined(__AVR_ATmega324P__) \
220 || defined(__AVR_ATmega324PA__) \
221 || defined(__AVR_ATmega325__) \
222 || defined(__AVR_ATmega325A__) \
223 || defined(__AVR_ATmega325P__) \
224 || defined(__AVR_ATmega3250__) \
225 || defined(__AVR_ATmega3250A__) \
226 || defined(__AVR_ATmega3250P__) \
227 || defined(__AVR_ATmega328__) \
228 || defined(__AVR_ATmega328P__) \
229 || defined(__AVR_ATmega329__) \
230 || defined(__AVR_ATmega329A__) \
231 || defined(__AVR_ATmega329P__) \
232 || defined(__AVR_ATmega329PA__) \
233 || defined(__AVR_ATmega3290__) \
234 || defined(__AVR_ATmega3290A__) \
235 || defined(__AVR_ATmega3290P__) \
236 || defined(__AVR_ATmega32C1__) \
237 || defined(__AVR_ATmega32HVB__) \
238 || defined(__AVR_ATmega32HVBREVB__) \
239 || defined(__AVR_ATmega32M1__) \
240 || defined(__AVR_ATmega32U2__) \
241 || defined(__AVR_ATmega32U4__) \
242 || defined(__AVR_ATmega32U6__) \
243 || defined(__AVR_ATmega406__) \
244 || defined(__AVR_ATmega48__) \
245 || defined(__AVR_ATmega48A__) \
246 || defined(__AVR_ATmega48P__) \
247 || defined(__AVR_ATmega644RFR2__) \
248 || defined(__AVR_ATmega64RFR2__) \
249 || defined(__AVR_ATmega640__) \
250 || defined(__AVR_ATmega644__) \
251 || defined(__AVR_ATmega644A__) \
252 || defined(__AVR_ATmega644P__) \
253 || defined(__AVR_ATmega644PA__) \
254 || defined(__AVR_ATmega645__) \
255 || defined(__AVR_ATmega645A__) \
256 || defined(__AVR_ATmega645P__) \
257 || defined(__AVR_ATmega6450__) \
258 || defined(__AVR_ATmega6450A__) \
259 || defined(__AVR_ATmega6450P__) \
260 || defined(__AVR_ATmega649__) \
261 || defined(__AVR_ATmega649A__) \
262 || defined(__AVR_ATmega6490__) \
263 || defined(__AVR_ATmega6490A__) \
264 || defined(__AVR_ATmega6490P__) \
265 || defined(__AVR_ATmega649P__) \
266 || defined(__AVR_ATmega64C1__) \
267 || defined(__AVR_ATmega64HVE__) \
268 || defined(__AVR_ATmega64M1__) \
269 || defined(__AVR_ATmega88__) \
270 || defined(__AVR_ATmega88A__) \
271 || defined(__AVR_ATmega88P__) \
272 || defined(__AVR_ATmega88PA__) \
273 || defined(__AVR_ATmega8HVA__) \
274 || defined(__AVR_ATmega8U2__) \
275 || defined(__AVR_ATtiny48__) \
276 || defined(__AVR_ATtiny88__) \
277 || defined(__AVR_ATtiny87__) \
278 || defined(__AVR_ATtiny167__) \
279 || defined(__AVR_AT90SCR100__) \
280 || defined(__AVR_ATA6289__)
281 
282 /* Use STS instruction. */
283 
284 #define wdt_enable(value) \
285 __asm__ __volatile__ ( \
286  "in __tmp_reg__,__SREG__" "\n\t" \
287  "cli" "\n\t" \
288  "wdr" "\n\t" \
289  "sts %0,%1" "\n\t" \
290  "out __SREG__,__tmp_reg__" "\n\t" \
291  "sts %0,%2" "\n\t" \
292  : /* no outputs */ \
293  : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
294  "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
295  "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
296  _BV(WDE) | (value & 0x07)) ) \
297  : "r0" \
298 )
299 
300 #define wdt_disable() \
301 __asm__ __volatile__ ( \
302  "in __tmp_reg__, __SREG__" "\n\t" \
303  "cli" "\n\t" \
304  "sts %0, %1" "\n\t" \
305  "sts %0, __zero_reg__" "\n\t" \
306  "out __SREG__,__tmp_reg__" "\n\t" \
307  : /* no outputs */ \
308  : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
309  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
310  : "r0" \
311 )
312 
313 
314 
315 #else
316 
317 /* Use OUT instruction. */
318 
319 #define wdt_enable(value) \
320  __asm__ __volatile__ ( \
321  "in __tmp_reg__,__SREG__" "\n\t" \
322  "cli" "\n\t" \
323  "wdr" "\n\t" \
324  "out %0,%1" "\n\t" \
325  "out __SREG__,__tmp_reg__" "\n\t" \
326  "out %0,%2" \
327  : /* no outputs */ \
328  : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
329  "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
330  "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
331  _BV(WDE) | (value & 0x07)) ) \
332  : "r0" \
333  )
334 
335 /**
336  \ingroup avr_watchdog
337  Disable the watchdog timer, if possible. This attempts to turn off the
338  Enable bit in the watchdog control register. See the datasheet for
339  details.
340 */
341 #define wdt_disable() \
342 __asm__ __volatile__ ( \
343  "in __tmp_reg__, __SREG__" "\n\t" \
344  "cli" "\n\t" \
345  "out %0, %1" "\n\t" \
346  "out %0, __zero_reg__" "\n\t" \
347  "out __SREG__,__tmp_reg__" "\n\t" \
348  : /* no outputs */ \
349  : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
350  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
351  : "r0" \
352 )
353 
354 #endif
355 
356 
357 
358 /**
359  \ingroup avr_watchdog
360  Symbolic constants for the watchdog timeout. Since the watchdog
361  timer is based on a free-running RC oscillator, the times are
362  approximate only and apply to a supply voltage of 5 V. At lower
363  supply voltages, the times will increase. For older devices, the
364  times will be as large as three times when operating at Vcc = 3 V,
365  while the newer devices (e. g. ATmega128, ATmega8) only experience
366  a negligible change.
367 
368  Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
369  500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
370  Symbolic constants are formed by the prefix
371  \c WDTO_, followed by the time.
372 
373  Example that would select a watchdog timer expiry of approximately
374  500 ms:
375  \code
376  wdt_enable(WDTO_500MS);
377  \endcode
378 */
379 #define WDTO_15MS 0
380 
381 /** \ingroup avr_watchdog
382  See \c WDT0_15MS */
383 #define WDTO_30MS 1
384 
385 /** \ingroup avr_watchdog See
386  \c WDT0_15MS */
387 #define WDTO_60MS 2
388 
389 /** \ingroup avr_watchdog
390  See \c WDT0_15MS */
391 #define WDTO_120MS 3
392 
393 /** \ingroup avr_watchdog
394  See \c WDT0_15MS */
395 #define WDTO_250MS 4
396 
397 /** \ingroup avr_watchdog
398  See \c WDT0_15MS */
399 #define WDTO_500MS 5
400 
401 /** \ingroup avr_watchdog
402  See \c WDT0_15MS */
403 #define WDTO_1S 6
404 
405 /** \ingroup avr_watchdog
406  See \c WDT0_15MS */
407 #define WDTO_2S 7
408 
409 #if defined(__DOXYGEN__) || defined(WDP3)
410 
411 /** \ingroup avr_watchdog
412  See \c WDT0_15MS
413  Note: This is only available on the
414  ATtiny2313,
415  ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
416  ATtiny25, ATtiny45, ATtiny85,
417  ATtiny261, ATtiny461, ATtiny861,
418  ATmega48, ATmega88, ATmega168,
419  ATmega48P, ATmega88P, ATmega168P, ATmega328P,
420  ATmega164P, ATmega324P, ATmega644P, ATmega644,
421  ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
422  ATmega8HVA, ATmega16HVA, ATmega32HVB,
423  ATmega406, ATmega1284P,
424  AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
425  AT90PWM81,
426  AT90USB82, AT90USB162,
427  AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
428  ATtiny48, ATtiny88.
429  */
430 #define WDTO_4S 8
431 
432 /** \ingroup avr_watchdog
433  See \c WDT0_15MS
434  Note: This is only available on the
435  ATtiny2313,
436  ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
437  ATtiny25, ATtiny45, ATtiny85,
438  ATtiny261, ATtiny461, ATtiny861,
439  ATmega48, ATmega88, ATmega168,
440  ATmega48P, ATmega88P, ATmega168P, ATmega328P,
441  ATmega164P, ATmega324P, ATmega644P, ATmega644,
442  ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
443  ATmega8HVA, ATmega16HVA, ATmega32HVB,
444  ATmega406, ATmega1284P,
445  ATmega2564RFR2, ATmega256RFR2, ATmega1284RFR2, ATmega128RFR2, ATmega644RFR2, ATmega64RFR2
446  AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
447  AT90PWM81,
448  AT90USB82, AT90USB162,
449  AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
450  ATtiny48, ATtiny88.
451  */
452 #define WDTO_8S 9
453 
454 #endif /* defined(__DOXYGEN__) || defined(WDP3) */
455 
456 
457 #endif /* _AVR_WDT_H_ */

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